The threshold voltage instability is a main reliability issue of Silicon Carbide MOSFET transistors. It is a critical parameter when it comes to give a failure in time rate for industrial power applications. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide degradation is studied and discussed in this paper. Complementary testing was performed with dynamic reliability on the gate and the results obtained are used to add insight to the current discussion of SiC MOSFET reliability standards. Additionally, test bench and characterization protocols are detailed.
Quentin Molin, Mehdi Kanoun and Christophe Raynaud and Hervé Morel
Conference: IEEE-nternational Conference on Industrial Technology (ICIT)
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