25 kV-50 Hz railway power supply system emulation for Power-Hardware-in-the-Loop testings

2021-08-11T16:56:14+02:00January 8th, 2019|Electronique de puissance & convertisseurs, Publications|

This paper presents a methodology to consider the impedance of a grid in power hardware in the loop (PHIL) experiments to validate power converter control in presence of harmonics or resonances in the network impedance. As the phenomena to emulate are in a large frequency range, the skin effect in conductors has to be taken into account. A procedure is developed to model the network.

Modelling of a 25 kV-50 Hz railway infrastructure for harmonic analysis

2021-08-11T16:56:29+02:00December 20th, 2018|Electronique de puissance & convertisseurs, Publications|

This paper presents a methodology for the modelling of a 25 kV-50 Hz railway infrastructure, for frequencies from 0 to 5 kHz. It aims to quantify the amplifications of current and voltage harmonics generated by on-board converters into the infrastructure. A circuit is developed to model the skin effect in the overhead line for time-domain simulations. A new approach, based on state space representation and transfer functions, is also proposed to analyse the interactions between trains.

PhD Quentin MOLIN “High Voltage SiC MOSFET Robustness study: threshold voltage shift and short-circuit behaviour”

2021-08-11T17:42:45+02:00December 17th, 2018|Electronique de puissance & convertisseurs, Phd|

This manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks.

SuperGrid Institute’s project selected for Grid2030

2021-08-11T16:30:13+02:00December 6th, 2018|Architecture & systèmes du supergrid, Evenement|

SuperGrid Institute and IMDEA joint forces with the support of REE, and created a consortium. This consortium was selected from more than 80 projects. Through the "Reduced Inertia Transient Stability Enhancement" (RITSE) project, SuperGrid Institute will strive to improve the transient stability of the AC networks by coordinating the use of batteries and HVDC links.

Design of a 1200 V, 100 kW Power Converter: How Good are the Design and Modelling Tools?

2021-08-11T16:56:54+02:00November 21st, 2018|Electronique de puissance & convertisseurs, Publications|

During the design of power converter, design mistakes must be avoided, especially for high voltage and high power converters. Simulation tools can be used to help the designers and limit the risks. This presentation will present a design flow approach used to design and validate a 1.2 kV – 100 kW DC-DC converter which was design from die to converter levels and started for a “blank page”. The presentation is organized in four parts. Firstly, the context of the work is introduced. Then, the simulation flow approach used to validate the design is presented. For this part, the presentation will focus on the system level simulation of one inverter, including the power modules. This part will highlight the main limitations of the current simulation tools found by the designers. In the third part, an enhanced approach is proposed to overcome the limitations and the first results are presented Finally, a conclusion will be presented.

Study of Turn-to-Turn Electrical Breakdown for Superconducting Fault Current Limiter Applications

2021-08-11T16:57:02+02:00November 2nd, 2018|Appareillage électrique haute tension, Publications|

The rational insulation design of a resistive superconducting fault current limiter (r-SCFCL) requires data gathered from experimental setups representative of the final apparatus. Therefore, an experimental study was performed to characterize the electrical breakdown (BD) of liquid nitrogen (LN2) in the peculiar conditions of a quenching superconducting device.

Packaging of 10 kV SiC MOSFETs: Trade-Off Between Electrical and Thermal Performances

2021-08-11T16:57:19+02:00October 25th, 2018|Electronique de puissance & convertisseurs, Publications|

SiC transistors can achieve blocking voltages of 10kV and more. This makes them especially attractive for energy transmission and distribution. Although SiC devices can in theory operate at high temperature (more than 200°C), the on-state resistance of SiC MOSFETs exhibits a strong dependency on the junction temperature. As a consequence, it is shown that these transistors must actually operate at a relatively low junction temperature (less than 100°C) to increase conversion efficiency and prevent thermal runaway. This requirement for high-performance cooling systems has consequences on the packaging technology: the corresponding power modules must both offer a high voltage insulation and a low thermal resistance. In particular, there is a trade-off in the thickness of the ceramic substrate located between the SiC devices and the cooling system. We propose a new substrate structure, with raised features, which improves the voltage strength of a substrate without increasing its thickness. This structure is demonstrated experimentally.

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