Low level FPGA MMC control
Pipelined bitonic sorting implemented on FPGA
Description
The best information to make the right selection at each time step is a sorted list of the submodules according their capacitor voltage value. Easier said than done, it is a challenge to sort 512 values in microseconds for all 6 arms.
Implemented on Xilinx FPGA, a low level control using a full sort is proposed. The Bitonic sorting algorithm is suited to FPGA due to is parallel nature. But in this case where 6 times 512 values have to be sorted, a direct implementation requires more space than available on the FPGA. We overcame this problem by pipelining the process, using the modular nature of the algorithm.
TRL SCALE
Advantages
- Full sorting
- 6 times 512 levels
- Tested in HIL
Applications
- MMC converter control
