Unlocking HVDC interoperability: register for our free webinar!
In this webinar, we will share our technical analysis of HVDC interoperability and present possible directions we can take moving forward.
In this webinar, we will share our technical analysis of HVDC interoperability and present possible directions we can take moving forward.
In this webinar, we will share our technical analysis of HVDC interoperability and present possible directions we can take moving forward.
We are currently analysing the experimental data issue from these power tests in order to write our report for the project.
We are currently analysing the experimental data issue from these power tests in order to write our report for the project.
Our CEO Hubert de la Grandière was interviewed recently by Jean-Marc Sylvestre on the set of Small is Smart! Watch the vidéo here!
Our CEO Hubert de la Grandière was interviewed recently by Jean-Marc Sylvestre on the set of Small is Smart! Watch the vidéo here!
This paper presents a novel single-ended fault identification algorithm for meshed High Voltage Direct Current grids.
This paper investigates the gate-driver design challenges encountered due to the fast switching of wide band-gap semiconductors (here, SiC MOSFETs) in the half-bridge configuration.
The experimental studies show the effects of the transformer construction and vector group (star/delta) on the common-mode currents through the gate drivers of SiC MOSFETs in a 100kW 1.2kV three-phase dual active bridge converter.
In this paper, a methodology is proposed to define the optimal rated power and number of PEBBs.